DRAMs are typically organized into rows and columns (bit lines), with a bit stored at their intersections. By addressing a particular row and column the stored bit can be read by a sense amplifier connected to a column.
As the DRAM size, and thus the number of bits stored in a DRAM, has increased, addressing it has become more complex. For example in the very early (small) DRAMs (nominally 1K or 2K bits) both the rows and columns coould be addressed using a single address word. However once DRAMs reached the size of nominally 4K bits (4096 bits), address words for the rows and columns were multiplexed on an address bus. In a nominally 4K memory, for example, 6 bits in an address defined one selected row out of 64 possible rows and a further 6 bits defined one selected column out of 64 possible columns.
In more recently designed large memories, for example in a 1 megabit memory, 10 address bits define a row followed by 10 bits which define a column. The 1K (1024) bits defined by 10 column address bits is called a "page", and selection of data from this datafield without changing row address is called "page mode" operation.
At the intersection of each row and column is a transistor and capacitor, called a bit storage cell. As the number of cells per unit semiconductor substrate area increased, the tolerable ratio of cell capacitance to bit line capacitance set a practical limit of 256 cells connected to a bit line sense amplifier. The memory was therefore divided into blocks or groups. In a nominally 1 megabit memory, for example, each vertical (column) bit line in the matrix was divided into 8 blocks or groups, each being associated with 256 horizontal so called word lines. All of the bits stored at the intersection of a word line and all of the vertical bit lines forms a page.
In a typical 1 megabit chip, therefore, there cannot be simply 1024 bit lines and 1024 word lines. Because of the aforenoted capacitance ratio limitation there will be 8 blocks, each block having 256 word lines and 512 columns. As each column must be associated with a sense amplifier, such a typical memory chip thus has 4096 sense amplifiers. Because there are only 10 bits in a column address, page size is limited to 1024 bits.
Also, importantly, because of the peak current requirements from the power supply when all of the sense amplifiers associated with a particular word are to be accessed, all sense amplifiers could not be active when a row (word line) address change occurred. Some groups or blocks of words remain in a quiescent state.
With further increase in size of DRAMs, more of the memory will remain inactive and the difference between the number of sense amplifiers required and the accessible page sizes will become larger. For example, in a 16 megabit DRAM memory built using 12 bits for each of row and column address, a nominally 4K bit page size will be obtained, although 64K or more sense amplifiers are used. Depending on the adopted number of refresh cycles, not all of the sense amplifiers will be active at any one time.
With increases in processor speed, the page mode has become very important because the computing cycle is too short to allow both row and column addresses to be changed in one processor cycle.